Intel · Chip · Filed Feb 6, 2026 · USPTO published Nov 12, 2026 · This week's release

Intel Files Patent for Graphics Chips That Split Into Custom-Sized Slices for Different Users

Intel describes a graphics chip that can be carved into uneven slices, giving each customer a different mix of AI math and video circuitry instead of identical portions.

By Patentlyze Team · Updated Nov 12, 2026 · 3 min read

A graphics chip divides its computing power into separate sections so multiple people can run heavy visual jobs at once. Drawing from patent filing US 2026/0359140 A1. — A graphics chip divides its computing power into separate sections so multiple people can run heavy visual jobs at once.All 63 drawings ↓

Publication number: US 2026/0359140 A1(US20260359140A1)
Applicant: Intel Corporation
Filed · Published: Feb 6, 2026 · Nov 12, 2026
Inventors: David Cowperthwaite, Kenneth Daxer, Jeffery S. Boles, Hema Chand Nalluri, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala
Status when we published: Waiting for an examiner
Document: 20 claims
US classification: 718/104
Parent application: Continuation of 17/827,373 (filed May 27, 2022)(17827373)

What Intel's flexible GPU slicing actually does

Ever rented a fixed-size storage unit, only to find your boxes fill the floor but leave the ceiling empty? Intel describes the same kind of waste on the graphics chips that data centers rent out to several customers at once. Today, a chip gets cut into equal, walled-off portions, and each portion has the same mix of parts. If your job leans hard on one kind of circuitry and barely touches another, the rest sits idle.

Intel's patent application describes cutting the chip into small building blocks first, then combining those blocks into custom-sized portions. One customer might get a big share of the math-heavy circuitry used for AI work, while another gets a different blend. To the computer running everything, each portion can show up as its own separate graphics device, so every customer sees what looks like a chip of their own.

From the filing · CLAIM 21

processing circuitry comprising functional units including vector engines and matrix engines, the processing circuitry configurable to be flexibly partitioned into compute partitions; and circuitry to compose composite partitions of the graphics processing unit from functional units of the compute partitions …

Translation: The chip uses special math engines that can be split up into custom groups.

How Intel mixes matrix and vector units per slice

The claims describe a graphics processing unit (GPU, the chip that handles graphics and a lot of AI work) built from two main kinds of circuitry. Vector engines are general-purpose number crunchers. Matrix engines are specialized for the grid-style math that AI models depend on. The chip's processing circuitry can be split into compute partitions, which act as small building blocks.

Extra circuitry then composes composite partitions out of those blocks. The key claim is that the composite partitions are asymmetric: they hold different proportions of each engine type. In one example, a first composite partition takes the vector engines from the first block, while a second takes the vector engines from the second block plus the matrix engines from both.

The filing also describes mixing other parts the same way. If each block holds a media engine (video encoding and decoding hardware) and a ray tracing unit (lighting-effect hardware), the media engines can go to one composite partition and the ray tracing units to the other.

Finally, a system interface presents each composite partition to the host computer:

As a separate sub-device of the chip,
As standard virtual functions (SR-IOV or scalable I/O virtualization, which are ways of making one piece of hardware look like several),
Or as fully distinct devices.

From the filing · THE ABSTRACT

The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

Translation: The resulting virtual chips do not need to be identical in their capabilities.

Why uneven GPU slices matter for cloud renters

If you use cloud services that run AI or video work, the chips behind them are usually shared by many customers at once. Intel's filing describes a way to size each customer's share to the job, so fewer circuits on an expensive chip sit unused. That could mean more work done per chip, which matters to anyone paying for that capacity.

Each slice can be presented to the host computer as its own device, which fits the way data center chips are already divided among tenants. The filing is framed around data center chips, so you are likelier to feel the effect through cloud services than through the graphics card in a gaming PC.

Intel's 54th filing we've tracked since May in the AI chip wars space follows one cutting visual AI costs and one resuming giant calculations.

Editorial take

Claim 21 is short and wide. It asks for a graphics chip with two named kinds of circuitry (vector engines for general number crunching, matrix engines for AI math), a way to split that circuitry into building blocks, and circuitry that combines those blocks into slices holding different proportions of each kind. It sets no numbers, no ratios and no sizes.

That breadth is the point of the filing. Any chip that builds uneven slices from those two engine types fits the wording. The other independent claims say "accelerator device" instead of GPU and add a method and a full computer system, so the same idea is claimed three ways. The narrower details, like sharing media and ray tracing units across slices or showing slices to the host as separate devices, sit in the follow-on claims.

Bottom line: this is a sensible plumbing patent for the people who rent chips by the slice. How much of the uneven-slice idea survives is up to the examiner, and the main payoff for you would be less wasted hardware behind cloud AI services.

Source: US 2026/0359140 A1 at the USPTO (PDF). Full patent text and figures are in the official publication.

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The drawings · 63 sheets

63 drawing sheets from US 2026/0359140 A1 · click any drawing to enlarge

Main computer parts that link processors and memory, drawing sheet 1 from US 2026/0359140 A1 — Sheet 1 Main computer parts that link processors and memory

Core sections inside a parallel graphics chip, drawing sheet 2 from US 2026/0359140 A1 — Sheet 2 Core sections inside a parallel graphics chip

Memory management parts that speed up screen rendering, drawing sheet 3 from US 2026/0359140 A1 — Sheet 3 Memory management parts that speed up screen rendering

Clustered processing units that prepare graphics data, drawing sheet 4 from US 2026/0359140 A1 — Sheet 4 Clustered processing units that prepare graphics data

Specialized calculation units built for fast AI math, drawing sheet 5 from US 2026/0359140 A1 — Sheet 5 Specialized calculation units built for fast AI math

Paired calculation blocks sharing internal chip memory, drawing sheet 6 from US 2026/0359140 A1 — Sheet 6 Paired calculation blocks sharing internal chip memory

Four execution zones arranged to share graphics memory, drawing sheet 7 from US 2026/0359140 A1 — Sheet 7 Four execution zones arranged to share graphics memory

Combined graphics chip setup with ray tracing engines, drawing sheet 8 from US 2026/0359140 A1 — Sheet 8 Combined graphics chip setup with ray tracing engines

Show the other 52 sheets

Connecting multiple central processors and graphics chips together, drawing sheet 9 from US 2026/0359140 A1 — Sheet 9 Connecting multiple central processors and graphics chips together

Linking graphics units to a computer processor through shared memory, drawing sheet 10 from US 2026/0359140 A1 — Sheet 10 Linking graphics units to a computer processor through shared memory

Moving the graphics accelerator interface directly onto the main chip, drawing sheet 11 from US 2026/0359140 A1 — Sheet 11 Moving the graphics accelerator interface directly onto the main chip

How an app hands off computing tasks to graphics hardware, drawing sheet 12 from US 2026/0359140 A1 — Sheet 12 How an app hands off computing tasks to graphics hardware

Managing virtual machine graphics tasks through a central supervisor, drawing sheet 13 from US 2026/0359140 A1 — Sheet 13 Managing virtual machine graphics tasks through a central supervisor

Sharing memory across main processors and graphics chips, drawing sheet 14 from US 2026/0359140 A1 — Sheet 14 Sharing memory across main processors and graphics chips

How graphics chips convert basic shapes into pixels, drawing sheet 15 from US 2026/0359140 A1 — Sheet 15 How graphics chips convert basic shapes into pixels

Software layers that let AI programs talk to graphics hardware, drawing sheet 16 from US 2026/0359140 A1 — Sheet 16 Software layers that let AI programs talk to graphics hardware

Internal computing blocks that power an AI-focused graphics processor, drawing sheet 17 from US 2026/0359140 A1 — Sheet 17 Internal computing blocks that power an AI-focused graphics processor

Linking multiple graphics chips directly to speed up data sharing, drawing sheet 18 from US 2026/0359140 A1 — Sheet 18 Linking multiple graphics chips directly to speed up data sharing

Steps an image-recognition AI uses to inspect picture data, drawing sheet 19 from US 2026/0359140 A1 — Sheet 19 Steps an image-recognition AI uses to inspect picture data

How the AI remembers earlier steps to predict what follows, drawing sheet 20 from US 2026/0359140 A1 — Sheet 20 How the AI remembers earlier steps to predict what follows

Training the AI on sample data before everyday use, drawing sheet 21 from US 2026/0359140 A1 — Sheet 21 Training the AI on sample data before everyday use

Different ways to divide heavy AI workloads across server chips, drawing sheet 22 from US 2026/0359140 A1 — Sheet 22 Different ways to divide heavy AI workloads across server chips

Smart network card components that handle data traffic for servers, drawing sheet 23 from US 2026/0359140 A1 — Sheet 23 Smart network card components that handle data traffic for servers

All-in-one chip parts for running trained AI models on devices, drawing sheet 24 from US 2026/0359140 A1 — Sheet 24 All-in-one chip parts for running trained AI models on devices

Main hardware parts that run programs and link to accessories, drawing sheet 25 from US 2026/0359140 A1 — Sheet 25 Main hardware parts that run programs and link to accessories

Combining central processing and graphics onto one shared chip, drawing sheet 26 from US 2026/0359140 A1 — Sheet 26 Combining central processing and graphics onto one shared chip

Specialized computing blocks that handle ray tracing and AI math, drawing sheet 27 from US 2026/0359140 A1 — Sheet 27 Specialized computing blocks that handle ray tracing and AI math

Dedicated memory and parallel compute units inside a modern GPU, drawing sheet 28 from US 2026/0359140 A1 — Sheet 28 Dedicated memory and parallel compute units inside a modern GPU

Parts that process and send video to screens, drawing sheet 29 from US 2026/0359140 A1 — Sheet 29 Parts that process and send video to screens

Multiple graphics tiles connected together to share onboard memory, drawing sheet 30 from US 2026/0359140 A1 — Sheet 30 Multiple graphics tiles connected together to share onboard memory

Replacing display hardware with networking for pure data center computing, drawing sheet 31 from US 2026/0359140 A1 — Sheet 31 Replacing display hardware with networking for pure data center computing

Chip cores that handle graphics math and images, drawing sheet 32 from US 2026/0359140 A1 — Sheet 32 Chip cores that handle graphics math and images

Internal layout of processing cores inside a graphics cluster, drawing sheet 33 from US 2026/0359140 A1 — Sheet 33 Internal layout of processing cores inside a graphics cluster

Hardware units that juggle parallel math tasks in each core, drawing sheet 34 from US 2026/0359140 A1 — Sheet 34 Hardware units that juggle parallel math tasks in each core

Grid of calculating units tailored for heavy matrix math, drawing sheet 35 from US 2026/0359140 A1 — Sheet 35 Grid of calculating units tailored for heavy matrix math

Building block tile packing multiple graphics clusters onto a chip, drawing sheet 36 from US 2026/0359140 A1 — Sheet 36 Building block tile packing multiple graphics clusters onto a chip

Binary formats for feeding instructions to the graphics chip, drawing sheet 37 from US 2026/0359140 A1 — Sheet 37 Binary formats for feeding instructions to the graphics chip

Routing graphics and video through a chip to the display, drawing sheet 38 from US 2026/0359140 A1 — Sheet 38 Routing graphics and video through a chip to the display

Ordering and steering rendering commands to 3D or video paths, drawing sheet 39 from US 2026/0359140 A1 — Sheet 39 Ordering and steering rendering commands to 3D or video paths

Software layers connecting an app down to the graphics chip, drawing sheet 40 from US 2026/0359140 A1 — Sheet 40 Software layers connecting an app down to the graphics chip

Sending chip designs from a lab to a factory, drawing sheet 41 from US 2026/0359140 A1 — Sheet 41 Sending chip designs from a lab to a factory

Linking two small chips across an embedded bridge, drawing sheet 42 from US 2026/0359140 A1 — Sheet 42 Linking two small chips across an embedded bridge

Stacking processor and memory chips on one base, drawing sheet 43 from US 2026/0359140 A1 — Sheet 43 Stacking processor and memory chips on one base

Swapping modular chip pieces onto interconnected foundation slabs, drawing sheet 44 from US 2026/0359140 A1 — Sheet 44 Swapping modular chip pieces onto interconnected foundation slabs

Combining processing, security, and display parts onto one all-in-one chip, drawing sheet 45 from US 2026/0359140 A1 — Sheet 45 Combining processing, security, and display parts onto one all-in-one chip

Splitting image tasks between fixed geometry and flexible color processors, drawing sheet 46 from US 2026/0359140 A1 — Sheet 46 Splitting image tasks between fixed geometry and flexible color processors

Distributing graphics workloads across an array of unified shader engines, drawing sheet 47 from US 2026/0359140 A1 — Sheet 47 Distributing graphics workloads across an array of unified shader engines

Routing graphics from the processor to a screen, drawing sheet 48 from US 2026/0359140 A1 — Sheet 48 Routing graphics from the processor to a screen

Sharing a single graphics chip across multiple virtual computers, drawing sheet 49 from US 2026/0359140 A1 — Sheet 49 Sharing a single graphics chip across multiple virtual computers

Splitting memory and 3D tasks between virtual graphics units, drawing sheet 50 from US 2026/0359140 A1 — Sheet 50 Splitting memory and 3D tasks between virtual graphics units

How the system stops virtual apps from accessing the display, drawing sheet 51 from US 2026/0359140 A1 — Sheet 51 How the system stops virtual apps from accessing the display

Running dashboard gauges and passenger screens from one graphics chip, drawing sheet 52 from US 2026/0359140 A1 — Sheet 52 Running dashboard gauges and passenger screens from one graphics chip

Independent video channels created for separate virtual screens, drawing sheet 53 from US 2026/0359140 A1 — Sheet 53 Independent video channels created for separate virtual screens

Using memory to let virtual apps update the display, drawing sheet 54 from US 2026/0359140 A1 — Sheet 54 Using memory to let virtual apps update the display

Dividing a chip into isolated compute zones for different users, drawing sheet 55 from US 2026/0359140 A1 — Sheet 55 Dividing a chip into isolated compute zones for different users

Linking two interconnected processor tiles inside a single device package, drawing sheet 56 from US 2026/0359140 A1 — Sheet 56 Linking two interconnected processor tiles inside a single device package

Connecting multiple chip parts to a shared memory pool, drawing sheet 57 from US 2026/0359140 A1 — Sheet 57 Connecting multiple chip parts to a shared memory pool

Splitting a graphics core down the middle for two users, drawing sheet 58 from US 2026/0359140 A1 — Sheet 58 Splitting a graphics core down the middle for two users

Resizing the split slices to give one user more power, drawing sheet 59 from US 2026/0359140 A1 — Sheet 59 Resizing the split slices to give one user more power

Grouping different computing blocks into custom chip partitions, drawing sheet 60 from US 2026/0359140 A1 — Sheet 60 Grouping different computing blocks into custom chip partitions

Sheets 61 to 63 are in the full USPTO filing.

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The drawings · 63 sheets

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